Formal Verification Engineer

About the Company

At Avaron, you get the security of permanent employment combined with the variety of working at different customers. We place specialists across everything from tech, IT and industry to project management and business support – and whatever the assignment, you have a consultant manager who is there for you and your development.

About the Role

You will join a technically advanced ASIC development environment in the telecom industry, where formal verification plays a key role in securing quality early in the design flow. In this role, you will help verify complex digital designs, confirm functional correctness, and uncover design issues before they move further into development.

You will work close to both design and verification teams in an environment where deep technical knowledge and careful analysis make a real difference. This is a strong opportunity for you if you enjoy complex RTL challenges and want to influence verification quality in sophisticated ASIC and SoC development.

Job DescriptionYou will work hands-on with formal verification of complex ASIC and RTL designs.

You will define and evaluate properties and assertions to verify functional correctness.

You will use SystemVerilog and SystemVerilog Assertions as part of the verification flow.

You will debug complex RTL behavior and analyze verification results to identify root causes.

You will collaborate closely with design and verification teams to resolve issues early in the development process.

You will contribute to verification work in ASIC and SoC development environments.

RequirementsExperience with formal verification of ASIC / RTL designs

Experience with property checking and assertion-based verification

Experience with SystemVerilog / SystemVerilog Assertions

Experience debugging complex RTL and verification results

Experience from ASIC or SoC development environments

Strong analytical skills and ability to work closely with design and verification teams

Nice to haveExperience with UVM-based verification

Experience with C/C++ reference modelling

Experience with MATLAB

Experience with SystemC

What We OfferPermanent employment at Avaron AB

Occupational pension

Wellness allowance of SEK 5,000 per year

Application

Selections are made on an ongoing basis – apply as soon as you can.