HW accelerator IP system designer

Company description:

Ericsson AB

Job description: Join our Team About this opportunity:

Do you want to expand the technical boundaries for large-scale parallel computation?  This is your opportunity to explore and shape the technology behind the next generation of digital processing at Ericsson! A high performing radio network requires dedicated HW acceleration to off-load the CPU system in performing time-bound tasks on a massive scale. You will help develop advanced hardware accelerators and processors, working with everything from early ideas and prototypes to hardware design and implementation. Your main focus will be 3GPP Layer 1 processing, with opportunities to explore AI/ML processing platforms as well. You will work across the full technology stack, gaining experience in software design, hardware simulators, tool development, hardware design and implementation  

This is a great opportunity if you are early in your career and eager to learn, develop your technical expertise, and make an impact in an innovative technology area. 

 

What you will do:

Analyse and profile existing solution from a performance perspective 

Propose and investigate new ideas to improve the Ericsson processing platform 

Co-design of software and hardware to maximize system performance 

Develop simulation environments to help software and hardware development 

Be part of building proof of concepts to try out and evaluate new ideas 

Be part of realizing new hardware components and bring them into products 

Track industry trends, academic research, and technology developments 

Build an international and cross discipline network to promote new ideas  

 

The skills you bring:

M.Sc. or Ph.D. with focus on hardware or software development 

A collaborative approach and a genuine interest in co-design of hardware/software 

A curiosity about emerging technology, industry developments, and academic research, together with a drive to turn new ideas into practical innovation. 

An interest in algorithm implementation and linear algebra.